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triSYCL / sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
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PLRAM support #218

Closed gogo2 closed 1 year ago

gogo2 commented 1 year ago

This adds support for PLRAM memory 'banks'. In most cases it is just cloning the implementation of DDR/HBM with minor adjustments.

I agree that sycl/include/sycl/ext/xilinx/fpga/memory_properties.hpp deserves some refactoring (and even more with plram case), but I didn't try to do that in this PR as I don't know if you have specific plans for that.

Ralender commented 1 year ago

seems good to me. except for the tests. you cant use https://github.com/triSYCL/sycl/blob/sycl/unified/master/sycl/test/vitis/simple_tests/ddr_bank_test.cpp as an example of how ddr and hbm banks are tested.