triSYCL / sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
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`xrt_piEventGetProfilingInfo` not implemented #224

Open keryell opened 1 year ago

keryell commented 1 year ago

The example from https://github.com/triSYCL/sycl/blob/sycl/unified/next/sycl/doc/GettingStartedXilinxFPGA.md#running-a-bigger-example-on-real-fpga is using

  queue q {property::queue::enable_profiling()};

and fails with

keryell@xsjsycl41:/var/tmp/rkeryell/SYCL/llvm/sycl/test/vitis/edge_detection ((03ee1150c1c7...))$ ./edge_detection data/input/eiffel.bmp
Calculating Max Energy... 
inputBits = 8 coefMax = 2 
Max Energy = 14 Bits 
Image Dimensions: [1024 x 1895]
Used Size: 1895x1024 = 1940480
Launching Kernel... 
pixel_rb size in submit: 1940480 
pixel_rb count in submit: 1940480 
Getting Result... 
pi_xrt: unimplemented: call to unimplemented function in XRT backend: pi_result xrt_piEventGetProfilingInfo(pi_event, pi_profiling_info, size_t, void*, size_t*)
terminate called without an active exception
Aborted