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SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
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Add AMD AIE1 CGRA support with ACAP++/AIE++ and ArchGenMLIR for FPGA
#237
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keryell
closed
10 months ago
keryell
commented
1 year ago
Add compiler support for AMD AIE1 CGRA.
Provide ACAP++ and AIE++ SYCL extensions for AMD AIE1.
Provide ArchGenMLIR tool for FPGA SYCL to automatically generate approximations for mathematical fixed-point functions to optimize hardware usage for low precision computations.