triSYCL / sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
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Add AMD AIE1 CGRA support with ACAP++/AIE++ and ArchGenMLIR for FPGA #237

Closed keryell closed 10 months ago

keryell commented 1 year ago