[SYCL] Add POCL support

It should be very simple to add support for POCL. Our kernels are already SPIR-df when we feed our FPGA target through. We just have some slight strangeness that we need to deal with for our HLS backend that's mixed in with some of the things we need for our SPIR-df transformations (mainly the kernel name hashing we do, we probably don't want or need that for POCL, but this is tied into the SYCL program_manager.cpp and the inSPIRation pass).

So briefly at a high level what should be done:

Create a new Clang driver flag or someway to notify the Clang driver to use a different ToolChain or Tool
This flag should also set up at least the define __SYCL_SPIRDEVICE_\, this is already done for the Xilinx FPGA target, you can grep over the Clang and SYCL directories for it.
Create a new Tool or ToolChain for POCL
Create a new script for POCL, this script will be much simpler than the sycl-xocc script. All it needs to do is run some Opt passes, mainly the ASFixer (this may change in the future) and the InSPIRation pass

And that should be it, but there may be one or two things that need some minor tweaking in the SYCL runtime as the XILINX_* specific flags are turned off.

Removing weird kernel name modifications:

Remove kernel name hashing from the InSPIRation pass and put it into it's own separate pass
This new pass should be added to the list of Opt passes ran in sycl-xocc or you'll probably break FPGA compilation
Alter the SYCL runtimes program_manager.cpp to only check for weird hashed names for kernels when it's a Xilinx device (perhaps even just a Xilinx FPGA device if that's possible).

However if you don't really care about one step compilation using a driver, I think all you'd probably need to do to get a SPIR-df kernel working with POCL using 2 step compilation is to compile the device side kernel with the __SYCL_SPIRDEVICE__ macro defined and run the ASfixer and InSPIRation pass over them. There may have to be 1 or 2 other tweaks in the runtime as the XILINX related macros aren't defined and it's not likely to be a Xilinx device that's targeted but they shouldn't be too big of a problem.

If someone intends to implement this and there's any more questions on it, feel free to ping me in a comment and I'll get back to you ASAP I'm aware it's not incredibly detailed and I'm happy to ping people to the right segments of code if I still can...

triSYCL / sycl

[SYCL] Add POCL support #52