re-investigate dual-port RAMs with dual-write and dual-read

tsalvo / varvara-fpga

implementation of Varvara / Uxn in FPGA

MIT License

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re-investigate dual-port RAMs with dual-write and dual-read #2

Closed tsalvo closed 1 month ago

tsalvo commented 5 months ago

I had a stash to look into dual-port RAMs for the stack and main RAM, using custom RAM definitions that translated to raw VHDL in pipelineC (ram.h). These RAMs would allow for 16-bit reads and writes, where both ports could be read or write at the same time if needed.

I had some trouble with simulation under GHDL when using these ram.h declarations though. perhaps there is a way around it?

More info: https://github.com/JulianKemmerer/PipelineC/wiki/Automatically-Generated-Functionality#rams

tsalvo commented 3 months ago

dev-2port-stack branch adds dual-port RAM for the stack without the GHDL simulation issues, but it increases build times by around 2x.

I'll keep this branch caught up with dev. perhaps future releases can come from this branch, while normal development would continue on dev, for faster iteration.

tsalvo commented 1 month ago

Dual-Port Stack RAM is released in 0.0.4 of openfpga-varvara. I'm going to close this issue for now