Closed d51r3verse closed 4 years ago
Try increase this delay in si5351.c
// Reset PLL need then band changes
static void si5351_reset_pll(uint8_t mask)
{
// Writing a 1<<5 will reset PLLA, 1<<7 reset PLLB, this is a self clearing bits.
// !!! Need delay before reset PLL for apply PLL freq changes before
chThdSleepMicroseconds(400);
si5351_write(SI5351_REG_177_PLL_RESET, mask | 0x0C);
}
If no help set DELAY_BAND_1 3
PS need use more correct delay intervals, not use I2S data ready interrupts step, i try rewrite this part.
Anyway set DELAY_NORMAL to 3 or 4 must help but it reduce sweep speed
I test it, if enter delay 1000 seems work good (as in 0.7)
chThdSleepMicroseconds(1000);
si5351 can`t reset PLL if enter new multiplier and try reset it directly after, need some delay, early for this used hack (sending data twice, but it not stable (do just delay on sending on I2C)), after add chThdSleepMicroseconds all work good, but timing depend from prev multiplirt values, in most cases 200 worked, i select 400, but seems need increase it to 900, best 1000.
Added
If enter delay 5000 look more better (better then 0.7), no big spike on band change in ch1
chThdSleepMicroseconds(5000);
Huge jitters suppressed.
@DiSlord Confirmed
chThdSleepMicroseconds(5000);
. 👍
Can you compare firmware 0.7 and this fixes? I hope that despite the fact that sweep speed faster stability has improved. Also as i see on screenshots exist artifacts on screen, it should be fixed at this PR https://github.com/ttrftech/NanoVNA/pull/126
Tested PR126(https://github.com/DiSlord/NanoVNA/commit/51b5cce0167f2955363059bcc7557ba75132d275) Screen updates faster than 0.4.0(50k~2.147G sweep /w all traces enabled)/Screen artifacts also gone💯
If I have more time, I wish to find another HW/SW nonlinear measure points. Thnx your contribution
sweep range combinations like below
Can't reproduce this wide&huge spikes on 0.7.0-20200223(7d2708a), and another variants(Hugen, QRP73 or so). DiSlord mixer workarounds fast. but need more tests.