This PR adds lo2s support for the heterogenous Alder Lake architecture.
Sadly, this did not make topdown available as simple perf events as I thought, but all other events work now.
this archive contains a simple example trace recorded with
lo2s -A -E cpu_core/cache-misses -E cpu_atom/cache-misses
One of the currently rather ugly things is that I'm creating a metric_class for every cpu (As every cpu can possibly have completely different metric_members) which looks like this in Vampir:
A fix would be using the same metric_class and writing 0 to events not supported on that core. I think this is a hack we have to take, but I would like prior input. Problems with this approach is that tracking which events are supported and which arent might be costly to do during measurements.
This PR adds lo2s support for the heterogenous Alder Lake architecture.
Sadly, this did not make topdown available as simple perf events as I thought, but all other events work now.
this archive contains a simple example trace recorded with
lo2s -A -E cpu_core/cache-misses -E cpu_atom/cache-missesOne of the currently rather ugly things is that I'm creating a
metric_classfor every cpu (As every cpu can possibly have completely differentmetric_members) which looks like this in Vampir:A fix would be using the same metric_class and writing 0 to events not supported on that core. I think this is a hack we have to take, but I would like prior input. Problems with this approach is that tracking which events are supported and which arent might be costly to do during measurements.
This fixes #216