Implement `rdcycle`, `rdtime`, and `rdinstret`

tum-ei-eda / etiss

Extendable Translating Instruction Set Simulator

https://tum-ei-eda.github.io/etiss/

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Implement `rdcycle`, `rdtime`, and `rdinstret` #105

Closed fpedd closed 2 years ago

fpedd commented 2 years ago

Would be nice if ETISS supported these (OVPsim and Spike offer them). Currently reading them returns 0.

See RISC-V User-Level ISA V2.2, 2.8 Control and Status Register Instructions, Timers and Counters for more info. They can then in turn be used to, for example, run performance tests on TensorFlow Lite Micro.

wysiwyng commented 2 years ago

@samanti-das and me will have a go at implementing this, stay tuned.

wysiwyng commented 2 years ago

Implemeted in #115. rdtime currently returns microseconds since Unix epoch, rdcycle and rdinstret return instruction count since simulator start.