Add architecture generated from CoreDSL 2 models

[wysiwyng]

This is a draft for a RV32IMACFD + Zicsr + Zifencei architecture model generated from CoreDSL 2 files at https://github.com/tum-ei-eda/etiss_arch_riscv.

The LR.W and SC.W instructions from the RV32A extension are implemented to pass the corresponding RISC-V test cases. They might still be unsuitable for an actual implementation.

In dhrystone, performance improvements of about 2x can be observed with this model.

The architecture is tested with the RISC-V test cases and this python tool to run them on ETISS.

Current compliance results:

• [x] RV32I
• [x] RV32C
• [x] RV32M
• [x] RV32D
• [x] RV32F
• [x] Zicsr
• [x] Zifencei
• [X] RV32A

TODO:

• [x] Make all tests pass
• [ ] Verify exception handling
• [x] Address JIT engine warnings
• [ ] Implement proper aliasing for xSTATUS, xIE, xIP CSRs
• [ ] Implement VirtualStruct properly
• [ ] Implement GDBServer properly
• [X] Implement RVA extension

[PhilippvK]

I think it would be a good idea to also update our Encoding.h to the latest spec: https://github.com/riscv/riscv-opcodes/blob/master/encoding.h