Exit simulation on loop-to-self instructions

[wysiwyng]

This adds a check to the main execution loop to detect loops to self, commonly used in embedded software to signal a program end. A loop to self in this case means an empty loop, in RISC-V assembly:

jal zero, #0

or

c.j #0

With this patch, ETISS terminates execution of the target program when a loop-to-self instruction is encountered. The main rationale behind this patch is to free up the currently misused instructions for simulation exit (e.g. EBREAK for RISC-V) for their normal purposes while providing a different termination mechanism.

[rafzi]

this might not be a good choice for an exit mechanism because there is embedded software that uses busy loops when all it does is react to interrupts. you mentioned today that a student is working on semi-hosting. IMO that would be the ideal way to handle this.

[wysiwyng]

While semihosting is a good way to handle the simulator exit, also with return codes, it is only available in target applications which have semihosting support compiled in. At least for RISC-V, many busy loops waiting for interrupts usually come in the form of:

1:
  wfi
  j 1b

with the wfi instruction putting the CPU to sleep until an interrupt occurs. This instruction sequence would not be caught by the above mechanism. As a compromise we could add a configuration option to enable exit on loop-to-self.