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tum-ei-eda / etiss

Extendable Translating Instruction Set Simulator
https://tum-ei-eda.github.io/etiss/
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Performance Improvements, Round 1 #22

Closed wysiwyng closed 4 years ago

wysiwyng commented 4 years ago

RISCVArch.cpp and RISCV64Arch.cpp updated to reflect latest changes in M2-ISA-R, removes unnessecary return statements after many instructions.

CMakeLists.txt for TCC is now properly applying optimizations to TCCLib compilation.

Note: Only RISCV (32 bit) is tested, as I do not have a test setup for 64 bit.

JoGei commented 4 years ago

Regarding your note: I have a simple RV64 example laying around in my fork. Maybe you want to try it out? https://github.com/JoGei/etiss/tree/vpu/examples/SW/riscv64

wysiwyng commented 4 years ago

Thanks, tested and works.

wysiwyng commented 4 years ago

I don't know the exact changes to m2isar, but at the very least the latest version correctly generates return statements after each instruction only when necessary.