As our instruction count measurements which the corstone300 target are quite unrealistic compared to the RISC-V ones I would like to validate those by comparing the FVP metrics with cycle/instruction counters on real hardware.
I think STM32 boards would be a good choice for this. The easiest approach would be adding support for PlatformIO, Zephyr or maybe Arduino using the Platform API.
Ideally we would have one board without extensions (e.g. Cortex-M0) and one with at least DSP instructions (Cortex-M7).
As our instruction count measurements which the corstone300 target are quite unrealistic compared to the RISC-V ones I would like to validate those by comparing the FVP metrics with cycle/instruction counters on real hardware.
I think STM32 boards would be a good choice for this. The easiest approach would be adding support for PlatformIO, Zephyr or maybe Arduino using the Platform API.
Ideally we would have one board without extensions (e.g. Cortex-M0) and one with at least DSP instructions (Cortex-M7).