Add (optional) CoreDSL2 attributes for overriding some seal5 settings

[PhilippvK]

Currently we need user-provided filters to choose which instructions or sets should (not) be processed by Seal5. See:

---
filter:
  sets:
    drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode]
  instructions:
    keep: [CV_MAC]

It would be great if one could (optionally) specify these details directly in the CoreDSL files like this using new Seal5Inst(Set)Attributes:

import "../rv_base/RV32I.core_desc"
InstructionSet XCoreVMac extends RV32I [[keep]] {
    instructions {
        CV_MAC [[keep]] {
            encoding: 7'b1001000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
            assembly: {"cv.mac", "{name(rd)}, {name(rs1)}, {name(rs2)}"};
            behavior: ...;
        }
        CV_MSU  [[keep]] [[skip_pattern_gen]] {
            encoding: 7'b1001001 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
            assembly: {"cv.msu", "{name(rd)}, {name(rs1)}, {name(rs2)}"};
            behavior: ...;
        }
    ...
    }
}
...

As motivated above, this could also be uses to tell Seal5 for which instructions PatternGen should not be used (i.e. due to incompatibilities).

[PhilippvK]

Another nice usecase would be for specifying metadata (such as versions) of instruction set extensions as usually done like this:

---
extensions:
  XCoreVMac:
    feature: XCVMac
    arch: xcvmac
    version: "1.0"
    experimental: true

In CoreDSL2 this could be alternatively done like this using custom attributes:

import "../rv_base/RV32I.core_desc"
InstructionSet XCoreVMac extends RV32I [[ver=1.0]] [[experimental]] [[arch=xcvmac]] {
    instructions {
        CV_MAC [[keep]] {
            encoding: 7'b1001000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
            assembly: {"cv.mac", "{name(rd)}, {name(rs1)}, {name(rs2)}"};
            behavior: ...;
        }
        CV_MSU  [[keep]] [[skip_pattern_gen]] {
            encoding: 7'b1001001 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
            assembly: {"cv.msu", "{name(rd)}, {name(rs1)}, {name(rs2)}"};
            behavior: ...;
        }
    ...
    }
}