Open GoogleCodeExporter opened 9 years ago
Output depicting the problem follows.
Turion Power States Optimization and Control - by blackshard - v0.xx.x
DRAM Configuration Status
Node 0 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=52
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 1 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=50
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 2 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=53
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 3 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=49
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 4 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=52
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 5 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=50
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 6 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=52
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Node 7 ---
DCT0:
Tcl=9 Trcd=9 Trp=9 Tras=24 Access Mode:1T Trtp=5 Trc=33 Twr=9 Trrd=4 Tcwl=7
Tfaw=20
TrwtWB=8 TrwtTO=7 Twtr=5 Twrrd=2 Twrwr=3 Trdrd=4 Tref=2 Trfc0=0 Trfc1=2 Trfc2=0
Trfc3=0 MaxRdLatency=50
DCT1:
Tcl=4 Trcd=5 Trp=5 Tras=15 Access Mode:1T Trtp=4 Trc=11 Twr=4 Trrd=4 Tcwl=5
Tfaw=0
TrwtWB=3 TrwtTO=2 Twtr=4 Twrrd=0 Twrwr=0 Trdrd=3 Tref=0 Trfc0=0 Trfc1=0 Trfc2=0
Trfc3=0 MaxRdLatency=0
Original comment by kszy...@gmail.com
on 11 Dec 2011 at 1:02
Original issue reported on code.google.com by
kszy...@gmail.com
on 11 Dec 2011 at 1:00