tuura / plato

A DSL for asynchronous circuits specification
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Fixed a bug where internals would not be parsed by Workcraft #52

Closed jrbeaumont closed 7 years ago

snowleopard commented 7 years ago

Thanks! That's what I hit during my demo in Tokyo :)

jrbeaumont commented 7 years ago

Oh I see. I can't believe I missed it before. I noticed it now, while doing some over the top testing of the concepts layout (now implemented)

snowleopard commented 7 years ago

@jrbeaumont Is it possible to add some tests, to make sure future commits do not break the conversion algorithm (testing that it correctly handles input, internal and output signals, as well as OR-causality)?

jrbeaumont commented 7 years ago

I'm sure it is, but we would need to test against an expected .g file, which may be large. Do you know of a smoother way to do it?

snowleopard commented 7 years ago

I think if you split the test into multiple smaller independent pieces, it will work well:

jrbeaumont commented 7 years ago

Ok, that sounds reasonable. I will make a start and think on some more simple tests. Possibly something where we use 2 different concept descriptions to produce the same output, as with a cElement.

snowleopard commented 7 years ago

@jrbeaumont Ah, good idea! Such a test could look like:

testCElement = c1 == c2
  where
    c1 == cElement a b c
    c2 == buffer a c <> buffer b c
snowleopard commented 7 years ago

You may need to implement an Eq instance for STG concepts, that would sort the list of arcs before doing the comparison.