search

tuura / plato

A DSL for asynchronous circuits specification
Other
12 stars 2 forks source link

Reordered validation in FSM translation and Refactored causality. #71

Closed jrbeaumont closed 7 years ago

jrbeaumont commented 7 years ago

So far, added AndCausality and OrCausality to Causality data type, which starts off #69, but we will need more discussion to include things like TimingAssumption.

Validation and translation are reordered for FSMs (#68). The initial states are checked first, and if valid, the translation is done. Following this, a check for signals with no interface declared, as well as for reachable never states. If this is valid, then the translation completes, outputting the .sg file. Otherwise, it outputs a handy error message, explaining either the problematic signal, or the never that is violated.

snowleopard commented 7 years ago

Thanks @jrbeaumont! See a bunch of comments above :)

jrbeaumont commented 7 years ago

@snowleopard: I have made these changes, including NonEmpty, excluding InvariantViolated (Invariant a), as we discussed.

I have also moved some things around while I've been at it for use with Workcraft, as I have been working on updating Workcraft for use with the new features concurrently. The major thing that will be coming up is changing errors to be output to STDERR, and everything else to STDOUT.

Have a look in your own time and let me know if you'd like any more changes made :)

jrbeaumont commented 7 years ago

@snowleopard: I have fixed those now :)

snowleopard commented 7 years ago

@jrbeaumont Thanks! One last touch (I'm surprised you didn't get a warning for redundant case).

jrbeaumont commented 7 years ago

@snowleopard: I did get an error, I just missed it and was working on something else, my bad haha.

snowleopard commented 7 years ago

Right. So, shall I merge this now?

jrbeaumont commented 7 years ago

I would wait until the CI checks pass. I have tested it on my mac, but it would be nice to be sure it definitely passes on everything.