tuura / plato

A DSL for asynchronous circuits specification
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Add asymmetric C-elements? #90

Open snowleopard opened 6 years ago

snowleopard commented 6 years ago

This is a low-priority feature request.

Asymmetric C-elements can currently be created using complexGate, but it may be convenient if there is a separate concept.

An example: ex a b c = buffer a c <> rise b ~> rise c. In this case b is only required in the set phase and is ignored in the reset phase.

jrbeaumont commented 6 years ago

It can be done quite nicely, and it works nicely too. Any signal can be used for b and it becomes required only for set. It will work nicely with bubble and dual.

snowleopard commented 6 years ago

We'll need to generalise this. Maybe discuss this with @danilovesky because he spent some time thinking about asymmetric C-elements while supporting them in Workcraft.

jrbeaumont commented 6 years ago

Would generalising with b being the asymmetric signal not work, or is this generalising for any number of inputs?

snowleopard commented 6 years ago

Supporting many inputs and in three roles: rise only (like b), fall only, and both (like a).

jrbeaumont commented 6 years ago

Ahh right. I'll talk to @danilovesky and haves think.