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tuura / scenco-core

Collection of encoding algorithms for conditional graphs
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Add technology mapping support #2

Closed snowleopard closed 8 years ago

snowleopard commented 8 years ago

See https://github.com/tuura/scenco/blob/master/TechnologyMapping.hs#L7-L8.

Current idea: ask logic synthesis tool like ABC to synthesise a bunch of boolean functions into a circuit and export it in Verilog/VHDL format.

allegroCoder commented 8 years ago

I have double checked whether ABC could spit out Verilog from the Boolean equations. It can, but unfortunately it’s technology independent. At least that is what’s written in the documentation of the tool (http://www.eecs.berkeley.edu/~alanmi/abc/). I will further explore this point though. In the worst case, I don’t think it would be too difficult to implement this feature in the worst case scenario.

allegroCoder commented 8 years ago

ABC can do the job which is currently done by espresso. Still need to check out pre-existing Haskell interfaces for HW synthesis though. However, it should not be too difficult switching to ABC.

snowleopard commented 8 years ago

ABC can do the job which is currently done by espresso.

Excellent, so we can stick to ABC. Unless you find a different hardware synthesis/technology mapping package available in Hackage.

allegroCoder commented 8 years ago

:+1: Sounds good to me!

allegroCoder commented 8 years ago

Fixed this issue! @snowleopard Could you close it, please?