Working with MMIO on aarch64 (Device Memory) means that we need to mess with some system registers and make sure that page table entries are set up correctly. To do this, we implemented a new variant of the CacheType enum in the twizzler_abi crate. This approach is the least invasive. In the future we could explore a more comprehensive description of the cacheing types for ARM. All mappings for MMIO use Device-nGnRnE.
Then we make sure that we can translate that generic description of the mapping type to some internal representation that is valid for MMIO on aarch64. On 64-bit ARM systems, this information lies in the MAIR_EL1 register which can be thought of as an array of memory types. We implemented an abstraction for managing state in that register to make it easier to work with.
The last bit is actually using this for MMIO. We demonstrate this by making sure that the drivers for UART and GICv2 map in the memory they use as Device Memory. We also add a check that stops us from initializing or using these drivers until after memory management is initialized.
Summary
create MemoryAttributeManager abstraction for managing MAIR_EL1
add MemoryMappedIO variant to CacheType
use MemoryAttributeManager and MemoryMappedIO in aarch64 pte code
Working with MMIO on aarch64 (Device Memory) means that we need to mess with some system registers and make sure that page table entries are set up correctly. To do this, we implemented a new variant of the
CacheTypeenum in thetwizzler_abicrate. This approach is the least invasive. In the future we could explore a more comprehensive description of the cacheing types for ARM. All mappings for MMIO use Device-nGnRnE.Then we make sure that we can translate that generic description of the mapping type to some internal representation that is valid for MMIO on aarch64. On 64-bit ARM systems, this information lies in the
MAIR_EL1register which can be thought of as an array of memory types. We implemented an abstraction for managing state in that register to make it easier to work with.The last bit is actually using this for MMIO. We demonstrate this by making sure that the drivers for UART and GICv2 map in the memory they use as Device Memory. We also add a check that stops us from initializing or using these drivers until after memory management is initialized.
Summary
MemoryAttributeManagerabstraction for managingMAIR_EL1MemoryMappedIOvariant toCacheTypeMemoryAttributeManagerandMemoryMappedIOin aarch64 pte code