A better explanation of inner sharable can be found here. According to the Arm Armv8-A Architecture Registers document the TLB invalidation instruction "applies to all PEs in the same Inner Shareable shareability domain as the PE that executes [that] System instruction."
This patch implements cache consistency for the data cache that may contain page table entries and the TLB which caches translations. From my understanding, the consistency is maintained system wide. So in ARM-speak to the point of coherency (PoC) and inner sharable. Page table entries are already marked inner sharable. https://github.com/twizzler-operating-system/twizzler/blob/167025d28e14e0029a239400081522ba49d69847/src/kernel/src/arch/aarch64/memory/pagetables/entry.rs#L26-L35
A better explanation of inner sharable can be found here. According to the Arm Armv8-A Architecture Registers document the TLB invalidation instruction "applies to all PEs in the same Inner Shareable shareability domain as the PE that executes [that] System instruction."
The implementation of the TLB management code drains the queue of TLB invalidations on an enqueue operation if the queue is full, and also drains the queue when it is dropped (much like
ArchCacheLineMgr). This is different from the x86 implementation and functionally from the generic code. This is due tofinishnever being called. https://github.com/twizzler-operating-system/twizzler/blob/0a4120a43058fd28f2d4383be056edbdfe070a31/src/kernel/src/memory/pagetables/consistency.rs#L48-L51Summary
unmapandmapoperations forArchContexttlbi)getstate