Open mkosunen opened 4 years ago
try to re-define _make_master by adding pcell will do, also parse pcell layout info in tech params
We have managed to implement this just adding primitives instead of layers in draw_mos method in tech class. Unfortunately we can not publish the result (yet) as it is not implemented with gpdk. (Ping @sporrasm ) . Anyway, this does not require changes in AnalogBase, which is good as it creates less variation in methodology.
@mkosunen Were you able to change to a new PDK successfully?
@AmrMohamedRashed Working on it. I'm kind of stuck redefining guard rings, but I've had my plate quite full, so maybe during the summer holidays... :)
@mkosunen I wish you the best of luck. I guess I have managed to map the BAG to work with gpdk045 if you faced any issue I might help but I still have to do some work first to be sure. have a nice summer vacation.
This is more like an heads up than an issue that would fit better into the proposed discussion forum than here, but I'll bring it up anyway.
With one of my students I'm ramping up a project where we will set up a BAG layout generators to use vendor specific device generators and the build kind of a version of AnalogBase around that. This simplifies the process definition and porting the designs from one process to another. Device generators is the easiest way to provide DRC clean and relatively well characterized devices, and current process setup basically requires re-write of those generators.
Naturally there is a need for hacking possibility too, but device generator based process definition would in my opinion lower the hreshold to take BAG into use. Let me know if you share interest to do this.