Closed mkosunen closed 2 years ago
@ayan-biswas Just to check, is master your current development branch or should I select some other target?
@ayan-biswas Just to check, is master your current development branch or should I select some other target?
Yes, master is the latest branch, and we don't see these issues. We just have to refresh Virtuoso sometimes to see all the updates.
Yes, master is the latest branch, and we don't see these issues. We just have to refresh Virtuoso sometimes to see all the updates.
@ayan-biswas I see, these features are only visible if you use parametrized pcells (like vendor provided transistor device generators or resistor generators) in a hierarchical design: parametrized pcell inside a templateDB inside a templateDB, AND the pcell requires CDF callbacks to be run. I do not know how much you have this kind of structures as for example when using analogBase you usually have none of these.
Anyway, as tested, the proposed fix works with the hierarchical design too, and otherwise the functionality is the same as before.
(we fare not using cybagoa, and I do not know if that affects something.)
@sporrasm Just to avoid unnecessary modifications/branch divergence, can you check if just refreshign Virtuoso without this hack would bring us the desired operation with one of our desings, and re-confirm whether we need this fix or not?
@sporrasm Just to avoid unnecessary modifications/branch divergence, can you check if just refreshign Virtuoso without this hack would bring us the desired operation with one of our desings, and re-confirm whether we need this fix or not?
Just tested it, unfortunately it doesn't seem to do the trick for us for some reason..
This pull request contains fixes that enable correct use of pcells in hierarchical bag layout.
@sporrasm , please elaborate the changes made/problems fixed if you wish.