FSqrt returns two valid responses for one input.

[ccelio]

TL;DR: I am sending one fsqrt request to hardfloat.DivSqrtRecF64. I get back one response the cycle after and then a second response back ~20 cycles later.

Waveform below.

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I am using commit (f38b8beeb3fbce40ee3d9c1e132c8f60ed05f4aa) which is what rocket-chip master uses (as well as the boom-devel branch of rocket-chip).

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Questions:

• Am I using DivSqrtRecF64 incorrectly?
• Is this fixed from more recent refactorings of DivSqrtRecF64?

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[ccelio]

I have set io.sqrtOp high because I assumed it was a DontCare if inValid is low. Reading ./docs/*.txt seems to imply that's the case.

In each clock cycle, input `inValid' is expected to be stable very early in   
the cycle.  The same is true of inputs `sqrtOp' and `b' whenever `inValid'    
is asserted.                                                                  

This particular error test-case would not trigger, but I'm not sure if that's just masking the issue.

[aswaterman]

Your assumptions about the interface seem to me to be correct.

It's impossible to tell where the bug is without the full waveform. It looks like there are other operations in flight before the operation in question, so is it not possible that the first response is to a previous request, rather than to the operation in question?

[ccelio]

Okay, looks like the problem is on my end.

I had counted requests and responses by eye and thought they were equal, but on closer inspection one request is held high waiting for ready to go high, but somehow misses a cycle of ready and stays high too long.

[aswaterman]

cool, thanks for sorting it out

[ccelio]

And thanks for the sanity check.