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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
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VCU118 fails to boot if using two cores #1009

Closed michael-etzkorn closed 3 years ago

michael-etzkorn commented 3 years ago

Impact: rtl|software

Tell us about your environment: Chipyard Version: Latest OS: CentOs7 Other:

Generating two cores instead of one for RocketVCU118 config.

What is the current behavior?

SD card errors out if using two cores. Does not if only using one.

What is the expected behavior?

SD card starts loading if two cores are used.

Other information

I'm using abstract config, two big rocket cores and then the VCU118 Tweaks. The SD card errors out. If I switch back to one big rocket core, the SD card will start loading.

abejgonzalez commented 3 years ago

Good catch. You probably need to change the VCU118 bootrom to be similar to Chipyards so that it only uses one core to run the bootrom.

VCU118 BootRom: https://github.com/ucb-bar/chipyard/blob/master/fpga/src/main/resources/vcu118/sdboot/head.S

TestchipIP BootRom: Bring all HARTs out of hang loop: https://github.com/ucb-bar/testchipip/blob/380583a2f8e83ffe4a419f4c64f80fe32a4e0460/src/main/resources/testchipip/bootrom/bootrom.S#L4-L17 Start up until the hang loop: https://github.com/ucb-bar/testchipip/blob/380583a2f8e83ffe4a419f4c64f80fe32a4e0460/src/main/resources/testchipip/bootrom/bootrom.S#L22-L38

michael-etzkorn commented 3 years ago

I was under the impression smp_pause handled only having one core execute vcu118 bootrom's main, but seems there will need to be some tweaks. Once we have a working solution, one of my teammates or I will submit a pull request ~

michael-etzkorn commented 3 years ago

After spending some time thinking about this today, I should add that only one set of print out instructions are visible, so its possible only one core is executing main, but something about having two cores is causing the SD card to timeout.

michael-etzkorn commented 3 years ago

Under sim, I can see that only one core is executing main. The other hangs at 0x10040. The smp_pause is working, but for some reason two cores can't load the SD card.

michael-etzkorn commented 3 years ago

Simulating VCU118 BootROM, only one of the cores begins executing main. It's not immediately obvious to me what the issue would be with two cores if the second core isn't involved in the boot process. Maybe an ILA on the sd card pins will help.

image

michael-etzkorn commented 3 years ago

I had forgotten that earlier a teammate wanted me to try overriding the bootrom. He couldn't get it to compile so he defined TL_CLK. We were using the overridden TL_CLK that was set to 1 MHz. Nothing would've worked. The 1 Rocket Core bitstream was just before this override happened. Two cores still didn't work after removing the define override, but it may be bc of other changes to sdboot or needing to run make clean. l have to get a fresh copy of sdboot and try two cores tomorrow.

michael-etzkorn commented 3 years ago

Yeah. This was introduced error on my end. Forgot I modified sdboot and never put it back to the way it was. smp_pause and smp_resume work as intended.

Yuxin-Yu commented 2 years ago

Hello, may I ask if your dual-core SOC starts normally? Can you tell me how you modified it?