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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
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Error when simulating asynchronous and rational clock crossing between front bus and system bus. #1016

Open ygkim912 opened 2 years ago

ygkim912 commented 2 years ago

Impact: rtl

Tell us about your environment: Chipyard Version: 1.5.0, Hash: b5d0131

What is the current behavior? Hi all,

When I was checking the asynchronous and rational clock crossing behavior of the front bus, I fount that the ready signal of the channel A and the valid signal of the channel D run in the system bus clock domain, not in the front bus clock domain. When I configured the following simple Rocket config with InitZero, it failed simulation.

class InitZeroAsyncRocketConfig extends Config(
  new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
    // Sbus
    new chipyard.config.WithSystemBusFrequency(400.0) ++ 
    new chipyard.config.WithSystemBusFrequencyAsDefault ++
    // Fbus
    new chipyard.config.WithFrontBusFrequency(600.0) ++
    new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++
    //new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing()) ++
    //
    new freechips.rocketchip.subsystem.WithNBigCores(1) ++
    new chipyard.config.AbstractConfig)

Simulation stopped in the TLMonitor with the message: Assertion failed: 'A' channel re-used a source ID ... I guess it due to the asynchronous behavior.

Please check the following waveform. Untitled (2)

Thanks for your help, Young.

jerryz123 commented 2 years ago

I suspect this is because the SerialAdapter widget is both a device on the MBus (which takes the sbus clock), and the FBus. I believe you need to set slaveCrossingType in SerialTLAttachParams (in testchipip) to be async or rational in this case.