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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
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[Boom Core] The I-cache assertion failed #1151

Closed Waxpple closed 2 years ago

Waxpple commented 2 years ago

Background Work

Chipyard Version and Hash

Release: 1.6.2 Hash: 481398

OS Setup

LSB Version: :core-4.1-amd64:core-4.1-noarch:cxx-4.1-amd64:cxx-4.1-noarch:desktop-4.1-amd64:desktop-4.1-noarch:languages-4.1-amd64:languages-4.1-noarch:printing-4.1-amd64:printing-4.1-noarch Distributor ID: RedHatEnterpriseServer Description: Red Hat Enterprise Linux Server release 7.9 (Maipo) Release: 7.9 Codename: Maipo

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

Simulation under sims/vcs is completely fine.

# Under sims/vcs
make debug CONFIG=SmallBoomConfig
./simv-chipyard-SmallBoomConfig-debug $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple

and the waveform of TestDriver.testHarness.chiptop.system.tile_prci_domain.tile_reset_domain.boom_tile.frontend.icache is like this: Imgur

Simulation under vlsi fails

make buildfile CONFIG=SmallBoomConfig
make sim-rtl-debug CONFIG=SmallBoomConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
/home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/simv +permissive +dramsim +dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +permissive-off /home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09_Full64; Runtime version S-2021.09_Full64;  Apr  2 03:41 2022
[UART] UART0 is here (stdin/stdout).
== Loading device model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' == 
== Loading system model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
Fatal: "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", 191091: TestDriver.testHarness.chiptop.system.tile_prci_domain.tile_reset_domain.boom_tile.frontend.icache: at time 2913500000 fs
$finish called from file "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", line 191091.
$finish at simulation time             29135000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2913500000 fs
CPU Time:      1.340 seconds;       Data structure size:  14.0Mb
Sat Apr  2 03:41:41 2022

Thevlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v verilog file:

`ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 <= 3'h1 | ~s1_valid) & ~reset) begin
          $fatal; // @[icache.scala 206:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_9 <= 3'h1 | ~s1_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at icache.scala:206 assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n"); // @[icache.scala 206:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS

The waveform and assertion failed Imgur Imgur

The trace of _T_5=s1_tag_hit_0 + s1_tag_hit_1 and s1_tag_hit_0= s1_vb_1 & tag_array_RW0_rdata_0 == s1_tag;

vcs/sims

Imgur

vlsi/

Imgur

The verilog file under vlsi and sims/vcs https://github.com/Waxpple/generated_src_SBC I think the two top.v Verilog files are identical, however, the two tag_array files are not identical.

Expected Behavior

I think the function should be the same, however, it will trigger the assertion.

Other Information

The original issue https://github.com/ucb-bar/hammer/issues/642

The result of running rv64ui-p-simple and rv64ui-p-add are the same, both of them failed. No response

Waxpple commented 2 years ago

https://github.com/ucb-bar/hammer/issues/642