Failed in RTL simulation on hwacha using verilator - Githubissues

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

https://chipyard.readthedocs.io/en/stable/

BSD 3-Clause "New" or "Revised" License

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Failed in RTL simulation on hwacha using verilator #1220

Closed YiKangOY closed 2 years ago

YiKangOY commented 2 years ago

Background Work

[X] Yes, I searched the mailing list
[X] Yes, I searched prior issues
[X] Yes, I searched the documentation

Chipyard Version and Hash

Release: 1.7.1 Hash: 9926642

OS Setup

Ex: Output of uname -a and lsb_release -a

Linux ca9ac4e7af1a 5.10.16.3-microsoft-standard-WSL2 #1 SMP Fri Apr 2 22:23:49 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux

No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 18.04.6 LTS Release: 18.04 Codename: bionic

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

I have configured environment as the documentation says. I ran make SUB_PROJECT=hwacha in sims/verilator

The log has been attached in the "Other information"

Expected Behavior

The make should worked.

Other Information

jerryz123 commented 2 years ago

HwachaConfig is not supported. Use HwachaRocketConfig.

https://github.com/ucb-bar/chipyard/blob/03083507d3c47ffb943bb4162f7b992082f84363/generators/chipyard/src/main/scala/config/RocketConfigs.scala#L31