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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.66k stars 656 forks source link

bug:change hwacha config #1234

Closed zzmsir closed 2 years ago

zzmsir commented 2 years ago

Background Work

Chipyard Version and Hash

Release: 1.7.1 Hash: 992664220d95edf610475031fd8a82d0cd743f7f

OS Setup

dont care

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

CONFIG=HwachaRocketConfig change DefaultHwachaConfig case HwachaNBanks => 4 >> case HwachaNBanks => 8 case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16) >> case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 32) Current Behavior:hwacha cannot load complete valid data sometimes meeting needed data, valid single cannot pull up(set 1) image

Expected Behavior

CONFIG=HwachaRocketConfig change DefaultHwachaConfig case HwachaNBanks => 4 >> case HwachaNBanks => 8 case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16) >> case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 32) Expected Behavior:hwacha can load complete valid data alltime meeting needed data, valid single must pull up(set 1) 1664526289(1)

Other Information

CONFIG=HwachaRocketConfig change DefaultHwachaConfig case HwachaNBanks => 4 >> case HwachaNBanks => 8 case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16) >> case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 32)

jerryz123 commented 2 years ago

I'm not sure what the error you are seeing is. Why do you expect a.valid to be high on those cycles?

zzmsir commented 2 years ago

I'm not sure what the error you are seeing is. Why do you expect a.valid to be high on those cycles?

I‘m testing hwachacase vec-daxpy,when a.valid is high,hwacha will load data from a.addr， a.addr is needed butnow a.valid is low

jerryz123 commented 2 years ago

The TL-A channel is a decoupled interface. Most likely on those cycles, the VMU intentionally desserts valid.

Are you seeing an erroring test case that can be traced back to this behavior?