search

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.64k stars 648 forks source link

Partial verilog re-elaboration #1350

Open jerryz123 opened 1 year ago

jerryz123 commented 1 year ago

Background Work

Feature Description

It would be great if partial verilog recompilation could be supported with CIRCT. The API could be like:

make CONFIG=RocketConfig re-elab-module MODULE=RocketTile

In this example, this command should regenerate the entire Chisel design, and check that the interface to RocketTile has not changed. If there has been no change to the module interface, then it should re-generate the RocketTile.sv only. If there was a change to the IO, then a warning for the user should be emitted.

Motivating Example

This enables some useful workflows for VLSI and FPGA-prototyping. Of course, the designer should be aware of the dangers of this approach.

tianrui-wei commented 1 year ago

I think cp --update would be a good candidate for this usage