Closed noahgaertner closed 1 year ago
It doesn't appear to be a config bug, the same behavior exists in MulticlockRocketConfig
- also have confirmed it does not exist in 1.8.1, so we're rolling back to that release for our chip, but I can help debug/isolate the issue if neccesary.
Reorder the WithAsynchonousRocketTiles
above the WithNMedCores
in your config
For context, the WithXRocketTiles
now modifies a local parameter for the tile, rather than global parameters, so those fragments must be added after tiles params are added
FYI those reported frequencies are only used by the fake "clock approximator" divideronlyclockgenerator used for RTL sim/FireSim. They otherwise have no bearing on the physical implementation of the chip, in which you'll need to integrate a PLL or a clock receiver.
ChipLikeRocketConfig
to show how a tapeout-ready config might appear.issue fixed by reordering config.
Background Work
Chipyard Version and Hash
Release: 1.9.0 Hash: 7475bfb
OS Setup
Ex: Output of
uname -a
+lsb_release -a
+printenv
+conda list
uname - alsb_release -a
printenv (w/o pdk proprientary info)
conda list
Other Setup
Ex: Prior steps taken / Documentation Followed / etc... skipped FireMarshal install b/c it resulted in a crash (also probably a bug, will file later)
Current Behavior
Config
results in
Expected Behavior
Tile Frequency should be 750MHz, and Input Reference Clock should also be 750MHz.
Other Information
No response