search

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.63k stars 645 forks source link

Dromajo is not work with 1.9.1 #1513

Open jimmysitu opened 1 year ago

jimmysitu commented 1 year ago

Background Work

Chipyard Version and Hash

Release: 1.91 Hash: 968b20

OS Setup

Distributor ID: Ubuntu Description: Ubuntu 20.04.6 LTS Release: 20.04 Codename: focal

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple run-binary

Ends with FAIL: Dromajo Simulation Failed with exit code: 8191 Here is the log, similar to #1323 

using random seed 1686203565
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 34359
== Loading device model file '/home/jmst/wrk/tmp/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' == 
== Loading system model file '/home/jmst/wrk/tmp/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
3 0x0000000000010040 (0x00000517) x10 0x0000000000010040 auipc   a0, 0x0
3 0x0000000000010044 (0xfc050513) x10 0x0000000000010000 addi    a0, a0, -64
csr_read: hartid=0 csr=0x305 val=0x0
csr_write: hardid=0 csr=0x305 val=0x0000000000010000
3 0x0000000000010048 (0x30551073)                        csrw    mtvec, a0
csr_read: hartid=0 csr=0x301 val=0x94112d
3 0x000000000001004c (0x301022f3) x5  0x800000000094112d csrr    t0, misa
[error] EMU PC 000000000001004c, DUT PC 000000000001004c
[error] EMU INSN 301022f3, DUT INSN 301022f3
[error] EMU WDATA 800000000094112d, DUT WDATA 800000000014112d
[error] EMU MSTATUS a00001800, DUT MSTATUS 00000000
[error] DUT pending exception -1 pending interrupt -1

Expected Behavior

It seems dromajo is not sync with the BOOM design, while I try spilke cosim, the cosim works right, which means my BOOM design is OK

I wonder if dromajo is already not support by chipyard any more?

Other Information

No response

jerryz123 commented 1 year ago

I don't plan on maintaining Dromajo further. Spike based cosimulation should be used from now on.