Illegal assignment pattern [IAP] error when using VCS-2014 for simulation

[fangrouli]

Background Work

• [X] Yes, I searched the mailing list
• [X] Yes, I searched prior issues
• [X] Yes, I searched the documentation

Chipyard Version and Hash

Release: 1.9.0 Hash: 7475bfb

OS Setup

System 1: Linux ... 5.19.0-45-generic #46~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC ... 20 x86_64 GNU/Linux Using Conda to set up, conda-lock = 1.4.0

System 2: Linux ... 2.6.32-754.el6.x86_64 #1 SMP ... 2018 x86_64 x86_64 x86_64 GNU/Linux Using Synopsys 2014.09

Other Setup

The .sv files are generated on the Ubuntu 22.04 system by command make verilog in sims/vcs/ directory. The generated files in chipyard.TestHarness.RocketConfig is copied to another terminal with CentOS 6 for simulation. The CentOS 6 system has GCC and G++ version of 4.7.2

Current Behavior

Generating the verilog for the default RocketConfig and copy to the VCS-located terminal. Source the synopsys source file. Running the Makefile with command make run. This is the Error log.

In summary, VCS compiler detect a lists of illegal assignment pattern in various .sv files generated, for example in Aomics.sv:

wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};   // @[Atomics.scala:42:8]

Expected Behavior

No error, successful compilation with a simv executable generated.

Other Information

I have already included systemverilog option in VCS command, so really not sure what is the cause of the error. Please point the error cause to me, thank you very much!

[jerryz123]

I would pose this question to the CIRCT devs, the SV emitted by CIRCT works with more modern tool versions. Perhaps there's some CIRCT flag that prevents this assignment pattern.

[fangrouli]

I would pose this question to the CIRCT devs, the SV emitted by CIRCT works with more modern tool versions. Perhaps there's some CIRCT flag that prevents this assignment pattern.

Alright, I will pose it to there then. Thankss!

[fangrouli]

The issue is opened at CIRCT side at #5424. Close this side for now.