Closed luming-xyz closed 1 year ago
Added: Command to use dhrystone test environment:
cd sims/verilator
make CONFIG=RocketConfig
./simulator-chipyard.harness-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
thank you
Delete Chipyard/.classpath_cache and retry?
Delete Chipyard/.classpath_cache and retry? It works, and now vivado is compiling, thank you very much!!!
Background Work
Chipyard Version and Hash
Release: 1.10.0 CentOS Linux release 7.9.2009
OS Setup
① I completed the "1.4.1 Initial Repository Setup" by following the documentation
② Then run the dhrystone program to test the environment and get the following results cd sims/verilator make CONFIG=RocketConfig ./simulator-chipyard.harness-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
③ When I tried running "10. Prototyping Flow" I got the error
cd fpga _make SUBPROJECT=vcu118 bitstream
Other Setup
No response
Current Behavior
Expected Behavior
I have searched the relevant materials but failed to find a solution. May I ask how I should troubleshoot this problem :)
Other Information
No response