Is the data in the inclusive L2 cache synchronized with the data in the DDR, or how can I enable the write-through function of the L2 cache?

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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

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Is the data in the inclusive L2 cache synchronized with the data in the DDR, or how can I enable the write-through function of the L2 cache? #1915

Open Yuxin-Yu opened 5 days ago

Yuxin-Yu commented 5 days ago

Background Work

[X] Yes, I searched the mailing list
[X] Yes, I searched the documentation

Feature Description

Motivating Example

jerryz123 commented 4 days ago

There is no write-through capability currently implemented.

For write-through support, you can write to the MBUS bypass mechanism if you enable it, note that this will be an incoherent write to backing memory.

Yuxin-Yu commented 4 days ago

Hi @jerryz123 ,Thanks for your reply. Do you have any plans to add write-through functionality? Also, could you be more specific about the MBUS bypass mechanism you mentioned? For example, which configuration code should be modified?