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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.66k stars 656 forks source link

Bump toolchains/riscv-tools/riscv-isa-sim from `824ecdf` to `aacfc53` #2084

Closed dependabot[bot] closed 1 month ago

dependabot[bot] commented 1 month ago

Bumps toolchains/riscv-tools/riscv-isa-sim from 824ecdf to aacfc53.

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dependabot[bot] commented 1 month ago

Superseded by #2092.