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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.66k stars 656 forks source link

Bump toolchains/riscv-tools/riscv-isa-sim from `824ecdf` to `88fc84d` #2092

Closed dependabot[bot] closed 3 weeks ago

dependabot[bot] commented 1 month ago

Bumps toolchains/riscv-tools/riscv-isa-sim from 824ecdf to 88fc84d.

Commits
  • 88fc84d Merge pull request #1839 from ved-rivos/issue_1838
  • 8566627 add missing sdt/sie interaction when writing mstatus directly
  • fa694e2 Merge pull request #1835 from joe-rivos/fix-ignored-attributes-warning
  • a93eb1b Fix ignored-attributes warning for unique_ptr declaration
  • aacfc53 Merge pull request #1834 from aap-sc/master
  • f0a0655 update encoding.h to get rid of erroneous define
  • See full diff in compare view


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dependabot[bot] commented 3 weeks ago

Superseded by #2111.