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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.66k stars 656 forks source link

Bump toolchains/riscv-tools/riscv-isa-sim from `824ecdf` to `2c67071` #2131

Open dependabot[bot] opened 4 days ago

dependabot[bot] commented 4 days ago

Bumps toolchains/riscv-tools/riscv-isa-sim from 824ecdf to 2c67071.

Commits
  • 2c67071 Merge pull request #1859 from ved-rivos/issue_1857
  • 64972b7 Add missing priv qualification to prev_virt
  • 4156e07 Merge pull request #1853 from arrv-sc/master
  • adafbd3 feat: add possibility for custom CSRs
  • fd0a927 Merge pull request #1848 from riscv-software-src/fix-1846
  • 1adf60f Fix FCSR accesses under Zfinx
  • ce71e75 Remove require_fs macro, as it is only used once
  • f0d4d42 Merge pull request #1830 from demin-han/master
  • 2688d17 Fix non-standard interrupt start position
  • 88fc84d Merge pull request #1839 from ved-rivos/issue_1838
  • Additional commits viewable in compare view


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