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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
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make failed when using VCS 2016 #691

Closed JunningWu closed 3 years ago

JunningWu commented 4 years ago

Impact: rtl

Tell us about your environment: Chipyard Version: branch master, Hash: 19152d3 OS: Linux chipyard-vm 5.4.0-49-generic #53~18.04.1-Ubuntu SMP Mon Sep 21 14:12:39 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux Other: Vmware

What is the current behavior?

I can simulate with verilator, when using VCS, after runing make or make debug

recompiling module data_arrays_0_0
recompiling module l2_tlb_ram
recompiling module Queue_36_inTestHarness
recompiling module UARTAdapter_inTestHarness
recompiling module cc_dir_ext
recompiling module split_cc_dir_ext
recompiling module split_data_arrays_0_ext
recompiling module split_tag_array_ext
recompiling module split_tag_array_0_ext
recompiling module split_data_arrays_0_0_ext
All of 191 modules done
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/mm.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/mm_dramsim2.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/remote_bitbang.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDRAM.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDTM.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimJTAG.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimSerial.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimUART.cc
g++ -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/uart.cc
cc1: warning: command line option '-std=c++11' is valid for C++/ObjC++ but not for C
/usr/bin/ld: /home/chipyard/software/synopsys/vcs2016/linux64/lib/vcs_save_restore_new.o: relocation R_X86_64_32S against undefined symbol `_sigintr' can not be used when making a PIE object; recompile with -fPIC
/usr/bin/ld: final link failed: Nonrepresentable section on output
collect2: error: ld returned 1 exit status
Makefile:104: recipe for target 'product_timestamp' failed
make[1]: *** [product_timestamp] Error 1
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
Make exited with status 2
Makefile:50: recipe for target '/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig' failed
make: *** [/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig] Error 2

What is the expected behavior?

Other information i guess something related to fPIC or PIE, where to disable Flags?

colinschmidt commented 4 years ago

This seems like an issue with your C compiler. What version of g++ are you using?

JunningWu commented 4 years ago 
g++ (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0
Copyright (C) 2017 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
abejgonzalez commented 4 years ago

This looks related: https://github.com/chipsalliance/rocket-chip/issues/1377. If you want to add/change flags you can refer to https://github.com/ucb-bar/chipyard/blob/19152d3b73f1c2255ce378501f6c01f9363b75e9/vcs.mk#L6-L10

JunningWu commented 4 years ago

@abejgonzalez According to Error while run "make -j4 run" in /vsim , I have changed VCS_CC_OPTS like this:

VCS_CC_OPTS = \
    -CC "-I$(RISCV)/include" \
    -CC "-I$(dramsim_dir)" \
    -CC "-std=c++11" \
    -CC "$(EXTRA_SIM_CC_FLAGS)" \
        -cpp g++-4.8 -cc gcc-4.8 \
        -LDFLAGS -Wl,-no-as-needed

the PIE error is solved, but I have got this Undefined reference error:

All of 192 modules done
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/mm.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/mm_dramsim2.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/remote_bitbang.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDRAM.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDTM.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimJTAG.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimSerial.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimUART.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -std=c++11 -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/uart.cc
cc1: warning: command line option '-std=c++11' is valid for C++/ObjC++ but not for C [enabled by default]
mm_dramsim2.o: In function `mm_dramsim2_t::init(unsigned long, int, int)':
mm_dramsim2.cc:(.text+0xcef): undefined reference to `DRAMSim::getMemorySystemInstance(std::string const&, std::string const&, std::string const&, std::string const&, unsigned int, std::string*)'
collect2: error: ld returned 1 exit status
Makefile:104: recipe for target 'product_timestamp' failed
make[1]: *** [product_timestamp] Error 1
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
Make exited with status 2
Makefile:54: recipe for target '/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig-debug' failed
make: *** [/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig-debug] Error 2
JunningWu commented 4 years ago

when changed gcc & g++ from 7.5 to 4.8, I could not build verilator, 

make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.debug'
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -O1 -std=c++11 -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -D__STDC_FORMAT_MACROS  -DTEST_HARNESS=VTestHarness -DVERILATOR -I/home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig -include /home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.plusArgs -include /home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig/verilator.h -include /home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.debug/VTestHarness.h   -c -o SimDRAM.o /home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig/SimDRAM.cc
g++: error: unrecognized command line option ‘-faligned-new’
VTestHarness.mk:74: recipe for target 'SimDRAM.o' failed
make[1]: *** [SimDRAM.o] Error 1
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/verilator/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.debug'
Makefile:138: recipe for target '/home/chipyard/work/chipyard/chipyard/sims/verilator/simulator-chipyard-RocketConfig-debug' failed
make: *** [/home/chipyard/work/chipyard/chipyard/sims/verilator/simulator-chipyard-RocketConfig-debug] Error 2
abejgonzalez commented 4 years ago

I would 1st try to get VCS working... I think the Verilator issue is different (I think that should work with gcc 7.5). The VCS issue seems that you can't find the DRAM sim header(s) (mm_dramsim2.h, mm.h) that is found in the tools/DRAMSim2 submodule. Do you have that submodule checked out? If so, then I would try to see if the header is included in the VCS compilation. It should be found in the generated-src for your project.

JunningWu commented 4 years ago

VCS is working well. And I added sims/vcs/generated-src/chipyard.TestHarness.RocketConfig directory to VCS, like this, which includes headers mm_dramsim2.h & mm.h 

VCS_CC_OPTS = \
    -CC "-I$(RISCV)/include" \
    -CC "-I$(dramsim_dir)" \
        -CC "-I$(build_dir)" \
    -CC "-std=c++11" \
    -CC "$(EXTRA_SIM_CC_FLAGS)" \
        -cpp g++-4.8 -cc gcc-4.8 \
        -CC "-LDFLAGS -Wl,-no-as-needed"

VCS compilation still failed with the same undefined reference error.

colinschmidt commented 4 years ago

Do you have access to a newer version of VCS? If you can get a 2018+ version of VCS you should be able to use a modern GCC.

abejgonzalez commented 4 years ago

Can you include the entire log from when VCS is invoked (cmd line up until the error msg)

While this is highly unlikely IMO, maybe the -CC "-I part is not working... since that should include the proper folder that holds the header files. I would try to man or find the guide for your VCS and double check that the -I works for your VCS version...

You can also try to manually run the VCS command and find another way to include the build folder with the headers.

JunningWu commented 4 years ago

According to vcs ug, -CC "-I works well for VCS 2016.

-CC <options>
   Works the same as -CFLAGS.
-CFLAGS <options>
   Pass options to C compiler. Multiple -CFLAGS are allowed. Allows
   passing of C compiler optimization levels.

The entire log after VCS command:

rm -rf csrc && vcs -full64 -notice -line -CC "-I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include" -CC "-I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2" -CC "-I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig" -CC "-std=c++11" -CC "" -cpp g++-4.8 -cc gcc-4.8 -CC "-LDFLAGS -Wl,-no-as-needed" /home/chipyard/work/chipyard/chipyard/tools/DRAMSim2/libdramsim.a /home/chipyard/work/chipyard/chipyard/riscv-tools-install/lib/libfesvr.a +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -error=noZMMCM -timescale=1ns/10ps -quiet -q +rad +v2k +vcs+lic+wait +vc+list -f /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/sim_files.common.f -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v -debug_pp +incdir+/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.top.v /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.harness.v /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.top.mems.v /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.harness.mems.v +libext+.v +define+VCS +define+CLOCK_PERIOD=1.0 +define+RESET_DELAY=777.7 +define+PRINTF_COND=TestDriver.printf_cond +define+STOP_COND=!TestDriver.reset +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN  -o /home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig-debug \
+define+DEBUG \
-debug_pp

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

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Lint-[NS] Null statement
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/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[NS] Null statement
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2

Lint-[SV-PIU] Package import statement in $unit scope.
/home/chipyard/software/synopsys/vcs2016/etc/sva/rec_ltl_classes_package.svp, 2
$unit, "SnpsSVA_classes::*"
  There is an import statement in $unit scope.
  Although this is legal as per the SystemVerilog LRM, it means that package 
  content will be shared without explicit import of the package.

Lint-[PCTIO-L] Ports coerced to inout
/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.top.v, 160334
"io_status_bits_blockC"
  Port "io_status_bits_blockC" declared as output in module "MSHR" may need to
  be inout. Coercing to inout.

Lint-[PCTIO-L] Ports coerced to inout
/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/chipyard.TestHarness.RocketConfig.top.v, 160335
"io_status_bits_nestC"
  Port "io_status_bits_nestC" declared as output in module "MSHR" may need to 
  be inout. Coercing to inout.

193 unique modules to generate
Generating code for _VCSgd_abP3b
Generating code for _VCSgd_reYIK
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Generating code for _VCSgd_SspYt
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Generating code for _VCSgd_KrGDi
192 modules and 2 UDPs read. 
recompiling package _vcs_unit__4082793690
recompiling package std
recompiling module EICG_wrapper
recompiling module GenericAnalogIOCell
recompiling module GenericDigitalGPIOCell
recompiling module GenericDigitalInIOCell
recompiling module GenericDigitalOutIOCell
recompiling module plusarg_reader
recompiling module SimDRAM
recompiling module SimSerial
recompiling module TestDriver
recompiling module TLMonitor
recompiling module TLMonitor_1
recompiling module TLMonitor_3
recompiling module TLFIFOFixer
recompiling module SimpleLazyModule
recompiling module SimpleLazyModule_1
recompiling module SimpleLazyModule_2
recompiling module SimpleLazyModule_3
recompiling module TLXbar_1
recompiling module TLXbar_2
recompiling module Queue
recompiling module Queue_1
recompiling module TLBuffer_1
recompiling module TLMonitor_12
recompiling module TLAtomicAutomata
recompiling module TLBuffer_2
recompiling module Repeater
recompiling module SimpleLazyModule_4
recompiling module PeripheryBus
recompiling module Queue_4
recompiling module Queue_5
recompiling module TLBuffer_3
recompiling module TLFIFOFixer_2
recompiling module SimpleLazyModule_5
recompiling module FrontBus
recompiling module TLXbar_4
recompiling module TLXbar_5
recompiling module Queue_6
recompiling module Queue_7
recompiling module TLBuffer_5
recompiling module TLMonitor_23
recompiling module TLAtomicAutomata_1
recompiling module Queue_8
recompiling module Queue_9
recompiling module TLBuffer_6
recompiling module SimpleLazyModule_6
recompiling module Queue_11
recompiling module Queue_12
recompiling module Repeater_1
50 of 192 modules done
recompiling module TLFragmenter_1
recompiling module SimpleLazyModule_7
recompiling module TLBuffer_8
recompiling module SimpleLazyModule_8
recompiling module Repeater_2
recompiling module SimpleLazyModule_9
recompiling module SimpleLazyModule_10
recompiling module Repeater_4
recompiling module SimpleLazyModule_11
recompiling module Repeater_5
recompiling module SimpleLazyModule_13
recompiling module PeripheryBus_1
recompiling module TLFIFOFixer_4
recompiling module ProbePicker
recompiling module QueueCompatibility
recompiling module AXI4IdIndexer
recompiling module Queue_13
recompiling module Queue_14
recompiling module TLToAXI4
recompiling module TLWidthWidget_4
recompiling module SimpleLazyModule_14
recompiling module MemoryBus
recompiling module TLMonitor_40
recompiling module Queue_15
recompiling module SourceA
recompiling module SourceB
recompiling module SourceC
recompiling module QueueCompatibility_21
recompiling module Atomics
recompiling module SourceD
recompiling module Queue_17
recompiling module SourceE
recompiling module SourceX
recompiling module SinkA
recompiling module SinkC
recompiling module Queue_21
recompiling module SinkD
recompiling module SinkX
recompiling module Directory
recompiling module BankedStore
recompiling module ListBuffer_2
recompiling module MSHR
recompiling module Scheduler
recompiling module TLFilter
recompiling module Queue_24
recompiling module Queue_25
recompiling module TLBuffer_9
recompiling module TLBuffer_10
recompiling module IDPool
recompiling module TLCacheCork
100 of 192 modules done
recompiling module TLJbar
recompiling module BankBinder
recompiling module SimpleLazyModule_15
recompiling module CoherenceManagerWrapper
recompiling module LevelGateway
recompiling module Queue_28
recompiling module TLPLIC
recompiling module CLINT
recompiling module DMIToTL
recompiling module TLDebugModuleOuter
recompiling module TLError_1
recompiling module TLBusBypass
recompiling module AsyncResetSynchronizerShiftReg_w1_d3_i0
recompiling module AsyncValidSync
recompiling module AsyncQueueSource
recompiling module AsyncQueueSink
recompiling module TLAsyncCrossingSource
recompiling module AsyncQueueSource_1
recompiling module TLMonitor_55
recompiling module TLMonitor_56
recompiling module TLAsyncCrossingSink
recompiling module AsyncQueueSink_2
recompiling module TLDebugModuleInnerAsync
recompiling module TLDebugModule
recompiling module TLMonitor_58
recompiling module TLXbar_8
recompiling module PMPChecker
recompiling module TLB
recompiling module MaxPeriodFibonacciLFSR_1
recompiling module DCacheModuleImpl_Anon_1
recompiling module DCacheDataArray
recompiling module AMOALU
recompiling module DCache
recompiling module ICache
recompiling module ShiftQueue
recompiling module PMPChecker_2
recompiling module TLB_1
recompiling module BTB
recompiling module Frontend
recompiling module Queue_29
recompiling module Queue_30
recompiling module Queue_31
recompiling module Queue_32
recompiling module TLBuffer_11
recompiling module IntSyncAsyncCrossingSink
recompiling module FPUDecoder
recompiling module RoundRawFNToRecFN
recompiling module FPUFMAPipe
recompiling module FPToInt
recompiling module IntToFP
150 of 192 modules done
recompiling module FPToFP
recompiling module RoundRawFNToRecFN_1
recompiling module FPUFMAPipe_1
recompiling module DivSqrtRecFN_small
recompiling module DivSqrtRecFN_small_1
recompiling module FPU
recompiling module HellaCacheArbiter
recompiling module Arbiter
recompiling module PTW
recompiling module IBuf
recompiling module CSRFile
recompiling module BreakpointUnit
recompiling module ALU
recompiling module MulDiv
recompiling module PlusArgTimeout
recompiling module Rocket
recompiling module RocketTile
recompiling module IntSyncCrossingSource_2
recompiling module IntSyncCrossingSource_3
recompiling module TLMonitor_60
recompiling module TLROM
recompiling module SerialAdapter
recompiling module TLMonitor_62
recompiling module UARTTx
recompiling module QueueCompatibility_22
recompiling module UARTRx
recompiling module ClockSinkDomain
recompiling module Queue_34
recompiling module DigitalTop
recompiling module cc_banks_0
recompiling module tag_array
recompiling module data_arrays_0_0
recompiling module l2_tlb_ram
recompiling module Queue_36_inTestHarness
recompiling module UARTAdapter_inTestHarness
recompiling module TestHarness
recompiling module cc_dir_ext
recompiling module split_cc_dir_ext
recompiling module split_data_arrays_0_ext
recompiling module split_tag_array_ext
recompiling module split_tag_array_0_ext
recompiling module split_data_arrays_0_0_ext
All of 192 modules done
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/mm.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/mm_dramsim2.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/remote_bitbang.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDRAM.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDTM.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimJTAG.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimSerial.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimUART.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/uart.cc
cc1: warning: command line option '-std=c++11' is valid for C++/ObjC++ but not for C [enabled by default]
mm_dramsim2.o: In function `mm_dramsim2_t::init(unsigned long, int, int)':
mm_dramsim2.cc:(.text+0xcef): undefined reference to `DRAMSim::getMemorySystemInstance(std::string const&, std::string const&, std::string const&, std::string const&, unsigned int, std::string*)'
collect2: error: ld returned 1 exit status
Makefile:104: recipe for target 'product_timestamp' failed
make[1]: *** [product_timestamp] Error 1
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
Make exited with status 2
Makefile:54: recipe for target '/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig-debug' failed
make: *** [/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig-debug] Error 2
JunningWu commented 4 years ago

run.log

JunningWu commented 4 years ago

Do you have access to a newer version of VCS? If you can get a 2018+ version of VCS you should be able to use a modern GCC.

I am not sure whether this error is related to older version gcc&g++?

JunningWu commented 4 years ago

I can compile when I comment mm.cc, mm_dramsim2.cc, SimDRAM.cc ,

recompiling module split_data_arrays_0_ext
recompiling module split_tag_array_ext
recompiling module split_tag_array_0_ext
recompiling module split_data_arrays_0_0_ext
All of 192 modules done
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
make[1]: Entering directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/remote_bitbang.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimDTM.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimJTAG.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimSerial.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/SimUART.cc
g++-4.8 -w  -pipe -fPIC -I/home/chipyard/work/chipyard/chipyard/riscv-tools-install/include -I/home/chipyard/work/chipyard/chipyard/tools/DRAMSim2 -I/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig -std=c++11 -LDFLAGS -Wl,-no-as-needed -O -I/home/chipyard/software/synopsys/vcs2016/include    -c /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/uart.cc
cc1: warning: command line option '-std=c++11' is valid for C++/ObjC++ but not for C [enabled by default]
/home/chipyard/work/chipyard/chipyard/sims/vcs/simv-chipyard-RocketConfig-debug up to date
make[1]: Leaving directory '/home/chipyard/work/chipyard/chipyard/sims/vcs/csrc'

and get the executable file simv-chipyard-RocketConfig-debug

JunningWu commented 3 years ago

Still unable to solve this problem.

abejgonzalez commented 3 years ago

Frankly, I'm not exactly sure what the issue is. The next thing I would check is that you have the DRAMSim2.h header pointed to with some -I and the libdramsim2.a library built and pointed to with -L.

JunningWu commented 3 years ago

After changing to a higher version VCS(2018), I can compile and run the simulation. So I guess the Chipyard project needs Ubunut18.04 & VCS2018, basically.

chipyard@chipyard-vm:~/work/chipyard/chipyard/sims/vcs$ ./simv-chipyard-RocketConfig-debug ../verilator/test/hello/hello
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
[UART] UART0 is here (stdin/stdout).
Hello, World!
1360
$finish called from file "/home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/TestDriver.v", line 158.
$finish at simulation time             22906500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 22906500 ps
CPU Time:      4.380 seconds;       Data structure size:   2.9Mb
Thu Dec  3 10:42:57 2020