Question about failed everything for RocketTinyCore

[LIUQyou]

Hi! I have a question about compiling programs for 32-bit cores. I tried to use Verilator to test Bare Metal RISC-V Programs with TinyCore( Is it 32-bit core, right?). First of all, I make TinyRocket with "make CONFIG=TinyRocketConfig". Then I got the simulation-XXX-Config file. Then I compile the benchmarks in Toolchain/riscv-tools, then I used ./simulation-XXX-Config dhrystone.riscv to test my tinycore. Then I failed. I thought it might be the problem of too small scratchpad memory( I am not sure, could you tell me if it is the reason?). Then write a very simple program, it fails as well, which makes me very confused. The following is my code:

int main(void){
int a = 1;
int b = 2;
if(a+b==3)
    return 0;
else
    return 2;
}

then I got

./simulator-chipyard-TinyRocketConfig ../../toolchains/riscv-tools/riscv-tests-liu/benchmarks/liu_test.riscv
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 35401
[UART] UART0 is here (stdin/stdout).
*** FAILED *** (tohost = 1337)
*** FAILED *** (code = 1337, seed 1615783452) after 144275 cycles

By the way, the make file I used is like the following:

#=======================================================================
# UCB VLSI FLOW: Makefile for riscv-bmarks
#-----------------------------------------------------------------------
# Yunsup Lee (yunsup@cs.berkeley.edu)
#

XLEN ?= 32

default: all

src_dir = .

instname = riscv-bmarks
instbasedir = $(UCB_VLSI_HOME)/install

#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------

bmarks = \
    liu_test\

#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------

RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf
RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld
RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
RISCV_SIM ?= spike --isa=rv$(XLEN)gc

incs  += -I$(src_dir)/../env -I$(src_dir)/common $(addprefix -I$(src_dir)/, $(bmarks))
objs  :=

define compile_template
$(1).riscv: $(wildcard $(src_dir)/$(1)/*) $(wildcard $(src_dir)/common/*)
    $$(RISCV_GCC) $$(incs) $$(RISCV_GCC_OPTS) -o $$@ $(wildcard $(src_dir)/$(1)/*.c) $(wildcard $(src_dir)/common/*.c) $(wildcard $(src_dir)/common/*.S) $$(RISCV_LINK_OPTS)
endef

$(foreach bmark,$(bmarks),$(eval $(call compile_template,$(bmark))))

#------------------------------------------------------------
# Build and run benchmarks on riscv simulator

bmarks_riscv_bin  = $(addsuffix .riscv,  $(bmarks))
bmarks_riscv_dump = $(addsuffix .riscv.dump, $(bmarks))
bmarks_riscv_out  = $(addsuffix .riscv.out,  $(bmarks))

$(bmarks_riscv_dump): %.riscv.dump: %.riscv
    $(RISCV_OBJDUMP) $< > $@

$(bmarks_riscv_out): %.riscv.out: %.riscv
    $(RISCV_SIM) $< > $@

riscv: $(bmarks_riscv_dump)
run: $(bmarks_riscv_out)

junk += $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(bmarks_riscv_hex) $(bmarks_riscv_out)

#------------------------------------------------------------
# Default

all: riscv

#------------------------------------------------------------
# Install

date_suffix = $(shell date +%Y-%m-%d_%H-%M)
install_dir = $(instbasedir)/$(instname)-$(date_suffix)
latest_install = $(shell ls -1 -d $(instbasedir)/$(instname)* | tail -n 1)

install:
    mkdir $(install_dir)
    cp -r $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(install_dir)

install-link:
    rm -rf $(instbasedir)/$(instname)
    ln -s $(latest_install) $(instbasedir)/$(instname)

#------------------------------------------------------------
# Clean up

clean:
    rm -rf $(objs) $(junk)

Could you tell me what should I do to compile my program? My goal is to use .riscv file like the following. ./simulator-chipyard-TinyRocketConfig hello.riscv

Thanks in advance, Best regards, Liu

[jerryz123]

Was your program able to run in spike?

[Yuxin-Yu]

Hello, have you solved is.I met the same problem. In the sim/inverter directory, I use the "riscv32-unknown-elf - *" toolchain to compile TinyRocketConfig, and then run the command

./simulator-chipard-TinyRocketConfig $RISCV/riscv32-unknown-elf/share/riscv-tests/benchmark/dhrystone.riscv

but I encountered an error，which like:

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1. Listening on port 36189 [UART] UART0 is here (stdin/stdout). [108000] %Error: chipyard.TestHarness.TinyRocketConfig.harness.v:25587: Assertion failed in TOP.TestHarness.ram.buffer_1.monitor %Error: /home/yyx/riscv/projects/chipyard/sims/verilator/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.v:25587: Verilog $stop Aborting...

Then I also increased the size of dtim and icache in TinyRocketConfig to 32KB. I ran again and encountered an error:

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1. Listening on port 36987 [UART] UART0 is here (stdin/stdout). FAILED (tohost = 1337) FAILED (code = 1337, seed 1666237832) after 117165 cycles

How can I fixed this? Thank you.

[michael-etzkorn]

but I encountered an error

Unfortunately, the TinyRocketCore is not well supported at the user level in Chipyard. Even though your DTIM is larger, you may need to adjust the linker script since it's possible your binary is still accessing memory it thinks it has but really doesn't.

Full disclosure: I have no idea what the fesvr failure codes mean and would have to dig around in the code to find where they come from and what they signify.

How can I fixed this? Thank you.

I'd migrate this discussion to #1188

[Yuxin-Yu]

OK.Thank you.

[Yuxin-Yu]

but I encountered an error

Unfortunately, the TinyRocketCore is not well supported at the user level in Chipyard. Even though your DTIM is larger, you may need to adjust the linker script since it's possible your binary is still accessing memory it thinks it has but really doesn't.

Full disclosure: I have no idea what the fesvr failure codes mean and would have to dig around in the code to find where they come from and what they signify.

How can I fixed this? Thank you.

I'd migrate this discussion to #1188

Again, I used the rv32 tool chain to run RV32RocketConfig, and also successfully ran dhrystone.riscv under the rv32 tool chain. Both are rv32 structured. What's the difference between them? Why does TinyRocketConfig have problems. RV32RocketConfig simulation resuls:

yyx@yyx-virtual-machine:~/riscv/projects/Chipyard-yyx/sims/verilator$ ./simulator-chipyard-RV32RocketConfig /home/yyx/riscv/projects/Chipyard-yyx/riscv32-tools-install/riscv32-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1. Listening on port 39591 [UART] UART0 is here (stdin/stdout). Microseconds for one run through Dhrystone: 492 Dhrystones per Second: 2030 mcycle = 246294 minstret = 202029

@michael-etzkorn

[michael-etzkorn]

I’d first confirm the linker script matches TinyConfig’s uarch. Especially, after hearing you were able to get farther by increasing the dtim size

---

发件人: Yuxin @.> 发送时间: Friday, October 21, 2022 2:29:36 PM 收件人: ucb-bar/chipyard @.> 抄送: Michael Etzkorn 明凯 @.>; Mention @.> 主题: Re: [ucb-bar/chipyard] Question about failed everything for RocketTinyCore (#827)

but I encountered an error

Unfortunately, the TinyRocketCore is not well supported at the user levelhttps://github.com/ucb-bar/chipyard/issues/1188 in Chipyard. Even though your DTIM is larger, you may need to adjust the linker script since it's possible your binary is still accessing memory it thinks it has but really doesn't.

Full disclosure: I have no idea what the fesvr failure codes mean and would have to dig around in the code to find where they come from and what they signify.

How can I fixed this? Thank you.

I'd migrate this discussion to #1188https://github.com/ucb-bar/chipyard/issues/1188

Again, I used the rv32 tool chain to run RV32RocketConfig, and also successfully ran dhrystone.riscv under the rv32 tool chain. Both are rv32 structured. What's the difference between them? Why does TinyRocketConfig have problems. @michael-etzkornhttps://github.com/michael-etzkorn

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