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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
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Question about directly emit `HasPeripheryPWMAXI4ModuleImp` or `HasPeripheryPWMTLModuleImp`. #89

Closed sequencer closed 5 years ago

sequencer commented 5 years ago

Instead of running a whole project of rocket-chip, I wonder if it is possible to just emit a minimal AXI4 Module for PWM, which is much easier to evaluate by Xilinx ZYNQ FPGAs or simply used as DUT for testing.

abejgonzalez commented 5 years ago

So far as I know, since the mixin is a diplomatic mixin (i.e. uses LazyModule and connects to the pbus), it requires that you build it with the entire system. One thing that you could do is make a config to build the smallest possible Rocket core/uncore.

Maybe someone else knows a better way to do this?

sequencer commented 5 years ago

Yes, I used to think using a "phantom" core to emit periphery only, however it's also too hard for me;( I'm not familiar with the rocketchip ecosystem and has no idea where to start reading.

abejgonzalez commented 5 years ago

The Berkeley folks here are trying to get some documentation up within the next couple of months to use this repo. However, Rocket-Chip is still a black hole of documentation. What I would try to do is just making your own small config or using a predone one like... https://github.com/freechipsproject/rocket-chip/blob/48b3e33c6cdb90bc9b86a7581c5be54f45c695e1/src/main/scala/system/Configs.scala#L59-L64

sequencer commented 5 years ago

Thank you! I’m going to check this config. Trying to understand the essence of diplomacy.

abejgonzalez commented 5 years ago

Seems like this is resolved for now. Will reopen if there are more questions or concerns.