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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
1.65k stars 653 forks source link

Add xiangshan core #911

Open HKalbasi opened 3 years ago

HKalbasi commented 3 years ago

There is a new risc v core named Xiangshan (github ) written in chisel. Is it possible to have it in chipyard? Will it be useful for chipyard and/or xiangshan and worth the needed efforts?

abejgonzalez commented 3 years ago

I don't think Chipyard folks are opposed to having a new core integrated w/ Chipyard. I think the main issue is maintenance and upkeep. We would need someone to own the code (i.e. we need to be able to reach out to them if something needs to be bumped/fixed/upgraded), add CI, etc. With that being said, I think comparing cores would be great!

HKalbasi commented 3 years ago

I opened an issue in xiangshan at the same time. From their comment I think they have works with more priority than maintaining it in Chipyard, and a "cleanup" is needed before integration, but in long-term I see Chipyard can make XiangShan more discover-able and removing some headache in using the core, and in other direction, Chipyard users will have another option, and more options is better.

So if you can provide some instructions on that thread about what should be done to make this integration, Xiangshan team (or community) may consider it in future.

redpanda3 commented 8 months ago

https://github.com/redpanda3/xiangshan-chipyard @HKalbasi