Support for Asynchronous Circuits

[sirinath]

Is it possible to add support for building asynchronous circuits and also provide some tutorial on how this can be done on Chisel.

[da-steve101]

My approach to this might be class Analog extends Node Have it as a double value that you can poke every clock for the emulator Verilog.scala shouldn't need much modification Could eventually have a PCB backend too and generate schematics and layouts Would need Analog to have various properties (capacitance/inductance between etc) ... would be alot of work but doable. Thoughts?

[sirinath]

I am not sure how this can be modeled internally but would be a good addition. Also if Chisel tool chain becomes available on Windows I can start using these features.

[schoeberl]

Are you mixing here two topics: asynchronous and analog circuits?

Asynchronous circuits are still digital circuits, but with local handshaking instead of a clock.

Martin

On 13 Aug, 2015, at 5:33, da-steve101 notifications@github.com wrote:

My approach to this might be class Analog extends Node Have it as a double value that you can poke every clock for the emulator Verilog.scala shouldn't need much modification Could eventually have a PCB backend too and generate schematics and layouts Would need Analog to have various properties (capacitance/inductance between etc) ... would be alot of work but doable. Thoughts?

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[sirinath]

No. Asynchronous logic. https://en.wikipedia.org/wiki/Asynchronous_circuit

No global clock or there is only a local clock. https://en.wikipedia.org/wiki/Clock_gating

[schoeberl]

Why does then the original post contain the words “Analog class” and “double value poking at every clock”?

Martin

On 17 Aug, 2015, at 15:05, Suminda Dharmasena notifications@github.com wrote:

No. Asynchronous logic. https://en.wikipedia.org/wiki/Asynchronous_circuit

No global clock or there is only a local clock. https://en.wikipedia.org/wiki/Clock_gating

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[da-steve101]

Sorry yes, had something else on my mind when i was writing it. Didn't read the question

[da-steve101]

I guess for async could just allow a register to have a null clock. Issue with it is how would the simulator work? You would need to specify the delays for everything.