After the Chisel compiler output'ed the following error message, it went ahead and generated incorrect Verilog:
[error]: All IO's must be ports (dir set): /_io_debug_vlen7 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen6 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen5 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen4 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen3 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen2 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen1 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
[error]: All IO's must be ports (dir set): /_io_debug_vlen0 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))
ucbjrl
commented
9 years ago
After the Chisel compiler output'ed the following error message, it went ahead and generated incorrect Verilog:
[error]: All IO's must be ports (dir set): /_io_debug_vlen7 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen6 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen5 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen4 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen3 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen2 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen1 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer)) [error]: All IO's must be ports (dir set): /_io_debug_vlen0 in class hwacha.Sequencer/ Chisel.UInt(width=11, connect to 1 inputs: ([Chisel.Reg] in hwacha.Sequencer))