java.lang.UnsupportedOperationException: empty.init after e8240d2 - improve verilog code generation

[ucbjrl]

Modules with no un-commented ports trigger the following crash:

[error] (run-main-0) java.lang.UnsupportedOperationException: empty.init
java.lang.UnsupportedOperationException: empty.init
    at scala.collection.TraversableLike$class.init(TraversableLike.scala:475)
    at scala.collection.mutable.ArrayBuffer.scala$collection$IndexedSeqOptimized$$super$init(ArrayBuffer.scala:47)
    at scala.collection.IndexedSeqOptimized$class.init(IndexedSeqOptimized.scala:129)
    at scala.collection.mutable.ArrayBuffer.init(ArrayBuffer.scala:47)
    at Chisel.VerilogBackend.emitDef(Verilog.scala:205)
    at Chisel.VerilogBackend$$anonfun$emitDefs$2.apply(Verilog.scala:461)
    at Chisel.VerilogBackend$$anonfun$emitDefs$2.apply(Verilog.scala:460)
    at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
 ~

[ucbjrl]

Closed by #546