Support for asynchronous resets in Verilog backend

[jwright6323]

It appears that Chisel does not support asynchronous resets. Can you add an option to use asynchronous resets in generated Verilog? This would help with our pin-limited designs (among others). An option to select the polarity of reset would also be useful, as most libraries only contain flops with active-low async reset/set pins.

Thanks, John

[ghost]

Hello,

Please find some comments how asynchronous resets in generated code should be implemented, to make sure that ASIC synthesis rules are not violated.

1. In the design resettable and non-resettable flops may exist together. It is important that these flops are described in separated always blocks.
2. The asynchronous reset condition must be the very first in the always block and it must constain only reset signal (e.g. if (rst) or if (~rst_n)).
3. Asynchronous reset signal should not be used for any logic outside always block (e.g. assign a = (rst) ? 1'b0 : b; is prohibited).
4. Reset polarity selection option is welcome, please note it is highly unlikely that both polarities coexist in single design.

Below is an example how generated code should look like:

always @(posedge clk or negedge rst_n)
begin
  if (~rst_n) begin //async-resettable flops
    flop1 <= FLOP1_RESET_VALUE;
    flop2 <= FLOP2_RESET_VALUE;
    //all async resettable flops
  end else //other conditions
end

always @(posedge clk)
begin
  if (rst) begin //sync-resettable flops (rst may be a local signal or any condition)
    flopA <= FLOPA_RESET_VALUE;
    flopB <= FLOPB_RESET_VALUE;
    //all other flops
  end else //other conditions
    //...
  flopC <= flopC_next; //this flop has no sync or async reset
end

Regards, Marek Ciepłucha

[jwright6323]

🎉freechipsproject/chisel3#1011 I guess I can close this now? Thanks @jackkoenig !