Sequential Memory behavior documentation is out-of-date

[ccelio]

The current SeqMem() semantics is, as I understand it:

val addr = UInt()
val enable = Bool()
val mySeqMem = SeqMem(1024, UInt(width = 32))
val data_out = mySeqMem.read(addr, enable)

where the data_out shows up on the next cycle (the internals of SeqMem register the address).

However, the Chisel manual (https://chisel.eecs.berkeley.edu/2.2.0/manual.html) specifies that the data_out must be registered.

val ram1r1w = Mem(UInt(width = 32), 1024, seqRead = true) 
val dout = Reg(UInt()) 
when (wen) { ram1r1w(waddr) := wdata } 
when (ren) { dout := ram1r1w(raddr) }

Meanwhile, the Chisel Tutorial 2.2 specifies that the address is what must be registered (https://chisel.eecs.berkeley.edu/latest/chisel-tutorial.pdf).

val ram1r1w = Mem(UInt(width = 32), 1024, seqRead = true)
val reg_raddr = Reg(UInt())
when (wen) { ram1r1w(waddr) := wdata }
val rdata = ram1r1w(reg_raddr)

[ccelio]

I'm closing this issue, since I'm conflating some confusion on Mem(seqRead=true) and SeqMem() [the upcoming Chisel3 version], which have different semantics.

However,

• the Chisel Manual is using out-dated semantics relative to the current Mem(seqRead=true).
• The Chisel3 upgrade guide will need to make this change in semantics clear.