Error in bits extraction

Hello!

This code is not working (for C backend and Verilog backend):

class Top extends Module {
        val io = new Bundle {
                val in = UInt(INPUT, width = 64)
                val data = UInt(OUTPUT)
        }
        val offset = Reg(UInt(width = 32))
        io.data := io.in(UInt(63) - offset, UInt(0))
}

From corresponding generated verilog code we can see where the error is:

module Top(input clk,
    input [63:0] io_in,
    output[63:0] io_data
);

  wire[63:0] T0;
  wire[63:0] T7;
  wire T1;                      <- T1 is 1 bit wide
  wire T2;                      <- T2 is 1 bit wide
  wire[31:0] T3;
  wire[31:0] T4;
  wire[31:0] T5;
  reg [31:0] offset;
  wire[63:0] T6;

  assign io_data = T0;
  assign T0 = T6 & T7;
  assign T7 = {63'h0, T1};      <- T1 is just 1 bit wide, but T7 is the mask for 64-bit num
  assign T1 = T2 - 1'h1;        <- T1, T2 is just 1 bit wide
  assign T2 = 1'h1 << T3;       <- meaningless op since T2 is 1 bit wide
  assign T3 = T4 + 32'h1;
  assign T4 = T5 - 32'h0;
  assign T5 = 32'h3f - offset;
  assign T6 = io_in >> 1'h0;

  always @(posedge clk) begin
    offset <= offset;
  end
endmodule

When I fix the verilog code by my hands to this (made T1 and T2 to be 64 bit wide):

... cut ...
  wire[63:0] T1;
  wire[63:0] T2;
... cut ...

the result is what is expected.

ucb-bar / chisel2-deprecated

Error in bits extraction #621