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ucb-bar / chisel2-deprecated

chisel.eecs.berkeley.edu
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Extract: avoid overflow causing by hi - lo + 1 #622

Closed ghost closed 8 years ago

ghost commented 8 years ago

This patch is related to issue #621

ghost commented 8 years ago

Can one of the admins verify this patch?

ghost commented 8 years ago

Also this was also wrong:

val mask = Op("-", widthInfer, Op("<<", widthInfer, UInt(1), hiMinusLoPlus1), UInt(1))

because widthInfer is equal to Node.widthOf(0) if width = -1, that's why it was interpreted as 1-bit wide wire.

ucbjrl commented 8 years ago

ok to test

ucbjrl commented 8 years ago

Unfortunately, this assumes width is available in the front end, and breaks existing code. Since both the C++ and Verilog backends know how to extract(), I think the best solution is to leave it up to them. Work on this is continuing in the extract621 branch.

ucbjrl commented 8 years ago

Closed by #649