Fix VCD output for registers

[ghost]

@schoeberl Could you please check the following example and examine VCD for Hz module. With your pull request I see on VCD for Hz module that input, output and reg are all raised at once.

import Chisel._

class Hz extends Module {
        val io = new Bundle {
                val input = Bool(INPUT)
                val output = Bool(OUTPUT)
        }
        val reg = Reg(init = Bool(false))
        when (io.input) {
                reg := Bool(true)
        }
        io.output := reg
}

class Top extends Module {
        val io = new Bundle {
                val input = Bool(INPUT)
                val output = Bool(OUTPUT)
        }
        val hz = Module(new Hz)
        hz.io <> io
}

class TopTests(c: Top) extends Tester(c) {
        step(1)
        poke(c.io.input, true)
        step(5)
}

object Top {
        def main(args: Array[String]): Unit = {
                chiselMain(args.slice(1, args.length), () => Module(new Top()), (c: Top) => new TopTests(c))
        }
}

By the way, examine all waves for Top and Hz for different module->dump() locations all give wrong results!

[schoeberl]

With your Top example I observe the following:

with Chisel 2.31 (still latest?): your example looks ok, but the BubbeFifo example has the too early display issue.

with Chisel 2.30: your Top example looks broken in two ways: io_input between Top and hz.io_input are different (should not be), and output of the register is one cycle to early. However, the BubbleFifo example is correct.

With my pull request applied your example looks broken similar to 2.30 (just a few cycles later). BubbleFifo is ok.

So all in all I am getting more and more confused here.

I've added (temporarily) your example (Top) into the repository (chisel-examples). You can build and run it with make top-test

The BubbleFifo with make fifo

Cheers, Martin

[ucbjrl]

Closed by #635