Cocotb directives in Verilog backend

[Martoni]

I'm using cocotb to write my testbench. Because it's in python and it's easier than writing verilog testbench. But to simulate verilog generated by chisel I have to modify the module generated to add timescale :

`timescale 1ps/1ps

In the top of source.

And vcd directive in the end of module

module MyModule (...);

[...]

`ifdef COCOTB_SIM
initial begin
  $dumpfile ("MyModule.vcd");
  $dumpvars (0, MyModule);
  #1;
end
`endif
endmodule

To dump vcd file.

Is there a way for generating it with the chisel backend (with a special option for example) ?

[aswaterman]

You can put this code in a separate .v file, which also 'includes the .v chisel emits.

On Thursday, March 10, 2016, Martoni notifications@github.com wrote:

I'm using cocotb https://github.com/potentialventures/cocotb to write my testbench. Because it's in python and it's easier than writing verilog testbench. But to simulate verilog generated by chisel I have to modify the module generated to add timescale :

`timescale 1ps/1ps

In the top of source. And this in module

module MyModule (...);

[...] `ifdef COCOTB_SIMinitial begin $dumpfile ("MyModule.vcd"); $dumpvars (0, MyModule);

1;end`endifendmodule

To dump vcd file.

Is there a way for generating it with the chisel backend (with a special option for example) ?

— Reply to this email directly or view it on GitHub https://github.com/ucb-bar/chisel/issues/674.

[Martoni]

@aswaterman Yes I do that, but with this solution I need to maintain one more source file. I wrote a little quick&dirty python script to add these lines just after the scala verilog generation if somebody is interested by it.